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Design High Speed Conventional D Flip-Flop using 32nm CMOS Technology ...
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[PDF] High speed and low power preset-able modified TSPC D flip-flop ...
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A Low-Power High-Speed Sense-Amplifier-Based Flip-Flop in 55 nm MTCMOS

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Figure 1 from Ultra Low-voltage Differential Static …
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Figure 8 from Ultra Low-voltage Differential Static D Flip-Flop for ...
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Figure 1 from A high-speed low-power D fli…

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High-Speed Flip-flop with Vertical Presentation
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RS Flip-flop Circuits using NAND Gates and NOR Gates

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