EDN

Design clock controllers for hierarchical test

Hierarchical test methodologies are being broadly adopted for large designs. They provide roughly an order of magnitude better ATPG (automatic test program generation) run time, reduce workstation ...
EDN

Clock-tree design made easy

Silicon Labs' new online timing utility, the Clock Tree Expert tool, was designed to enable embedded developers to generate sophisticated, streamlined clock tree block diagrams within minutes, ...
Dezeen

SWNA designs clock that doubles as an emergency kit

Seoul-based design studio SWNA has created a clock that incorporates an emergency kit filled with tools, which can be used in the event of a natural disaster. SWNA was approached by Korea Gyeonggido ...
Dezeen

Studio Ayaskan designs clock that rakes sand to illustrate the ripples of time

London design duo Studio Ayaskan has created a clock, which rakes sand in hypnotic, concentric circles to mark the passage of time. The Sand project is a nod to Japanese rock gardens, called ...
Semiconductor Engineering

Designing A Better Clock Network

Laying the proper clock network architecture foundation makes all the difference for the best performance, power, and timing of a chip, particularly in advanced node SoCs packed with billions of ...